Write a complete VHDL code to implement 8-bit Bidirectional Universal Shift Register with the following pins: Asynchronous Master Reset 8-bit Input (PP6P5P4P3PPP) 8-bit Output (Q7Q6Q5Q4Q3QQQo) CLK input (positive edge trigger) 2-bit Mode Select Input (SSo) to select from 4 synchronous operations as according to the next table DSL: Serial Input Data for Shift Left. DSR: Serial Input Data for Shift Right. S So 0 0 0 1 1 0 1 1 Mode Of Operation Hold Shift Right Shift Left Parallel Load You have to submit two files: 1. A VHDL code to implement your design. [4 points] 2. A testbench file to simulate and test your design. (You have to cover all possible cases) [4 points]