Question: Write a module in Vivado and look at the RTL schematic. Does the module reflect the functionality of MUX shown below? If not, how do

Write a module in Vivado and look at the RTL schematic.

Write a module in Vivado and look at the RTL schematic. Does the module reflect the functionality of MUX shown below? If not, how do you fix it? Write a test bench to test the modified MUX design. What to submit: Modified Verilog code, testbench, and the simulation waveforms in one pdf file

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