Question: Write a parametric Verilog module for computing out=ax2+bx+c. a, b, and c are three 4-bit signed parameters with the default value of a= -4 ,b=

Write a parametric Verilog module for computing out=ax2+bx+c. a, b, and c are three 4-bit signed parameters with the default value of a= -4 ,b= 3,and c= -3. x is a WL-bit signed input. The output out is registered using the clock signal CLK. (b) Write a testbench for your design. Demonstrate the output waveform for the following test stimuli. 4b1001, 4b0001, and 4b1111.

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