Write a Python program cache.py to simulate reading a direct$-$mapped cache or an n$-$way set associative cache. In this simulator, we are only interested in hits and misses, not in the word values being read. This program simulates the cache behavior $($using the cache scheme selected by the user$)$ for a sequence of memory accesses of $4-$byte words, using $32-$bit memory addresses.

Input

Your program should use Argparse Links to an external site. and support the following arguments:

$--$type: The type of cache. Valid options are d for direct$-$mapped and s for set associative cache. Note that the set associative cache must also specify the additional parameter $--$nway to configure the number of ways.

Error handling: If the nway parameter is not included for a set associative cache simulation, print the error message Set associative cache requires a valid $--$nway value

$--$cache$\_$size: The total cache size in bytes. This value must be a power of $2.$ The cache size in bytes does not include the valid and tag bits. For a set associative cache, this size represents the combined size of all of the sets.

Error handling: If the value is not a power of two, print the error message Cache size must be a power of $2$

$--$block$\_$size: The size of a block in bytes. This value must be a power of $2.$ This block size does not include the valid and tag bits.

Error handling: If the value is not a power of two, print the error message Block size must be a power of $2$

Error handling: If the block size is greater than the total cache size, print the error message Block size must be no greater than total cache size

$--$memfile: The input text file that contains the sequence of memory accesses. Each line of the input file is a memory address in hexadecimal format.

Error handling: If the input file is not present, print the error message Unable to open input file

Example usage:

python$3$ cache.py $--$type$=$d $--$cache$\_$size$=256--$block$\_$size$=64--$memfile$=$mem$1.$txt

Note: When first launched, your program must verify if an input configuration is possible for a given cache type. If the input configuration is not possible $($e$.$g$.$ invalid cache type, invalid cache size, or invalid block size$),$ print the error message specified above to the screen and exit the program.

Output

The program should produce a single output text file with the filename cache.txt$.$ For each memory access there should be a corresponding line in the output text file containing the following pipe $(|)$ separated values:

AccessedMemoryAddress$($hex$)|$TagBits$($binary$)|$IndexBits$($binary$)|$HITorMISSorUNALIGNED

Example output line: $27405950|0010011101000000010110010|10|$MISS

At the end of this output file, put a single line denoting the hit$/$miss rate:

hit rate: calculated value