Write a Self$-$Diagnosis $($Built$-$in self$-$test$)$ test$-$bench that is able to exhaustively tests the $4-$bit comparator. testbench.sv

$1//$ Code your testbench here

$//$ or browse Examples

module comp$\_4\_$str$\_$tb$()$;

endmodule

design.sv

$//$ Code your SV$/$Verilog Design

module comp$\_4\_$str

$($ lt$,$ eq$,$ gt$,$ A$,$ B$)$;

input $[3$:$0]A,B$;

output lt$,$ gt$,$ eq;

wire

eq$0,$ eq$1,$ lto, lt $1,$ gt$0,$ gt$1,$w$1,$w

$0$ ;

$9$ comp$\_2\_$str

M$1(1$t$1,$ gt $1,$ eq$1,$ A $[3$:$2],$ B $[3$:$2]$

;

$10$ comp$\_2\_$str

M$0(1$t$0,$ gto, eq$0,$ A $[1$:$0],$ B $[1$:$0]$

;

and a$1($w$1,$ eq$1,$ gt$0)$;

or ol $($gt$,$gt$1,$w$1)$;

and a$0($w$0,$ eq$1,$ lto$)$;

or $00(1t,1t1,w0$;

and ax $($eq$,$ eq$1,$ eq$0)$;

endmodule

module

comp$\_2\_$str$(1$t$,$ gt$,$ eq$,$ A$,$ B$)$ ;

input $[1$:$0]A,B$;

output lt$,$ gt$,$ eq;

wire w$1,$ w$2,$w$3,$w$4,$ w$5,$ w$6$;

not $N1(w6,A[1])$;

not N$2($w$7,$A$[0])$;

and A$1($w$1,$ w$6,$ B$[1])$;

and A$2($w$2,$w$7,$w$6,$B$[0])$;

and $A3($w$3,$ w$7,$ B$[1],$ B$[0])$;

xnor $x1(w4,B[1],A[1])$;

xnor $x2(w5,B[0],A[0])$;

and A$4($eq$,$w$4,$w$5)$;

or $01($lt$,$w$1,$w$2,$w$3)$;

nor N$3($gt$,$ lt$,$ eq$)$;

endmoduleExhaustively compares the actual output of the module with the expected output for every test case andmessages the pass and failure of any test case.