Write a structural Verilog module (gates netlist) for the following circuit: When writing your module, assume the following gate propagation delays: - NOT: 1 time unit - NOR: 2 time units Use the box below to type your verilog module: Q2 Verilog Test Benches 4 Points Write a Verilog test bench file for the module in Question 1 using the following test patterns: - Initially, apply AB=00 - After 7 time units (counting from initial time), apply AB=01 - After 14 time units (counting from initial time), apply AB=11 - Stop simulation at time =25 time units. Use the box below to type your Verilog test bench module: Enter your answer here Use the upload button below to upload the waveform of your test bench (in PDF): (]) Please select file(s) Write a behavioral Verilog module for the following circuit using assign statement: When writing your module, assume the following gate propagation delays: - NOT: 1 time unit - NOR: 2 time units Use the box below to type your Verilog module: Q4 Verilog Test Benches 4 Points Write a Verilog test bench file for the module in Question 3 using the following test patterns: - Initially, apply AB=10 - After 5 time units (counting from initial time), apply AB=00 - After 14 time units (counting from initial time), apply AB=10 - After 21 time units (counting from initial time), apply AB=11 - Stop simulation at time =30 time units. Use the box below to type your Verilog test bench module: Enter your answer here Use the upload button below to upload the waveform of your test bench (in PDF)