Question: i need the test bench Write a structural Verilog module (gates netlist) for the following circuit: When writing your module, assume the following gate propagation

i need the test bench

Write a structural Verilog module (gates netlist) for the following circuit: When writing your module, assume the following gate propagation delays: - NOT: 1 time unit - NOR: 2 time units Use the box below to type your Verilog module: Enter your answer here Q2 Verilog Test Benches 4 Points Write a Verilog test bench file for the module in Question 1 using the following test patterns: - Initilly, apply AB=00 - After 7 time units (counting from initial time), apply AB=01 - After 14 time units (counting from initial time), apply AB=11 - Stop simulation at time =25 time units. Use the box below to type your Verilog test bench module: Enter your answer here

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