Question: Q1 Structural Verilog Modeling 3 Points Write a structural Verilog module (gates netlist) for the following circuit: When writing your module, assume the following gate

Q1 Structural Verilog Modeling 3 Points Write a structural Verilog module (gates netlist) for the following circuit: When writing your module, assume the following gate propagation delays: - NOT: 1 time unit - NOR: 2 time units Use the box below to type your Verilog module: Enter your answer here

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