Write a "test bench" in EDA playground to test fully this design as follows:

$//$Moore FSM

module myMoore$($input clk$,$ reset, x$,$

output y$)$;

$//$state encodings

parameter s$0=2\text{'}$b$00,$ s$1=2\text{'}$b$01,$ s$2=2\text{'}$b$10$;

$//$state variables

reg $[1$ : $0]$ state, nextstate;

$//$state register always block

always @$($posedge clk$,$ posedge reset$)$

if $($reset$)$ state s$0$;

else state nextstate;

$//$next state always block

always$\_$comb

case $($state$)$

s$0$ : nextstate $=$ x $?$ s$0$ : s$1$;

s$1$ : nextstate $=$ x $?$ s$2$ : s$1$;

s$2$ : nextstate $=$ x $?$ s$0$ : s$1$;

default : nextstate $=$ s$0$;

endcase

$//$output logic

assign y $=($state $==$ s$2)$;

endmodule