Write a verilog behavioral code for a design with 4 bit inputs (in1) and 6 bit output (out1), with module name "tester2". The output conditions are

1) When input has greater number of 1's then output should be appended with 2'b11 along with input

2)  When input has less number of 1's then output should be appended with 2'b00 along with input

3) When input has equal number of 1's then output should be appended with 2'b01 along with input

4) Design the test bench such that every scenario is completely tested.

Note:- Kindly just provide the running verilog code along with the test bench for the design. No need to show the output