In the following Verilog Code, A, B, C, and D are registers that are 0 at time = 4 ns. If A changes to 1 at time 5 ns, make a table showing the values of A, B, C, and D as a function of time until time = 18 ns. Include deltas. Indicate the times at which each process begins executing.
always @(A)
begin
B <= #5 A;
C <= #2 B;
end
always
begin
wait(B);
A <= ~B;
D <= ~A ^ B;
end