Write a Verilog code for a synchronous counter with synchronous reset.This counter can count up and count down.When the counter counts up,the counting range is from 0 to 10 (0,1,2.....,9,10,0,1.....).When the counter counts down,the counting range is from 10 to 0 (10,9,.....1,0,10,9,....).The up_down signal is used to implement up counting (up_down=1)or down counting (up_down=0).The clock signal is active high and output is set to 0 if reset signal is high