A synchronous 4-bit UP/DOWN binary counter has a synchronous clear signal CLR and a synchronous load signal LD. CLR has higher priority than LD. 

Both CLR and LD are active high. D is a 4-bit input to the counter, and Q is the 4-bit output from the counter. UP is a signal that controls the direction of counting. If CLR and LD are not active and UP = 1, the counter increments. If CLR and LD are not active and UP 0, the counter decrements. All changes occur on the falling edge of the clock.

(a) Write a behavioral Verilog description of the counter.
(b) Use the foregoing UP/DOWN counter to implement a synchronous modulo 6 counter that counts from 1 to 6. This modulo 6 counter has an external reset, which, if applied, makes the count = 1. A count enable signal CNT makes it count in the sequence 1, 2, 3, 4, 5, 6, 1, 2, . . ., incrementing once for each clock pulse. You should use any necessary logic to make the counter go to count = 1 after count = 6. The modulo 6 counter counts only in the UP equence. Provide a textual/pictorial description of your approach.
(c) Write a behavioral Verilog description for the modulo-6 counter in part (b).