Question: write a verilog code Simulate clock in AVM with test bench parameters as set Add print statements to the test bench to monitor the outputs

write a verilog code

Simulate "clock" in AVM with test bench parameters as set Add print statements to the test bench to monitor the outputs Add a clock cycle time limit to the test bench Set test bench parameters to their synthesizable values and rerun Note the approximate time it takes to reach clock cycle time limit in each case

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