Write a VHDL $$code that implements an FSM $$for a$3-$bit down counter that transitions through the terms of $$a sequence

where the terms are defined as$$an$=2$an$-1-$an$-2.$The initial terms are inputs into the

VHDL $$design and make sure synchronous active high reset is $$used to $$reset the

FSM$.$The initial terms are $3-$bit non$-$zero positive values such that a$1>$a$2.$Write a test bench to $$test the counter's reset and test the counter with two sets of $$inputs$.$

Comment your VHDL $$code and test bench. Please test the simulation and check the waveform. test a$1=6,$a$2=4$for the first case and a$1=5,$ a$2=3$ for the second case.

Case $1$ answers should be $6,4,2,0,6.$ Case $2$ answers should be $5,3,1,5.$ Coding in Vivado so please test it and show a waveform picture.