Question: : Write a VHDL code to design 3 to 8 Decoder with enable using 1 - when else 2 - select with 3 - process

: Write a VHDL code to design 3 to 8 Decoder with enable using
1- when else 2- select with 3- process (case statement)
In each case, you need to create a new project, write your code then compile and simulate your
design. Show the RTL viewer in each case, and record the propagation delay

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