Write a VHDL file (block_c.vhd) with the dataflow description of block_c.

A car manufacturer is to incorporate a driver fatigue detection system based on the frequency and duration of blinks.

The system consists of the following elements:

1.An oscillator generating a 200 ms period clock signal, clk.

2.A reset signal, rst, active at high level for 300 ms when the car is started.

3.An infrared camera that analyzes the driver's eyes. It has an output, blink_in, which provides a '1' if it detects closed eyes and a '0' otherwise. This signal is synchronous with clk.

4.A visual alarm on the dashboard recommending the driver to rest, and it is triggered by the signal fatigue_out.

5.A loud audible alarm triggered by signal danger_out.

6.An FPGA that receives clk, rst and blink_in and generates fatigue_out and danger_out

Structure of the system like this:

All input signals (blink_in, clk y rst), outputs (fatigue_out y danger_out) and internal signals (thirty_s y sleep_s) are 1-bit signals, except signal accum_s which is a 12-bits bus. The system is divided into four blocks, which are detailed below.

Block_c is responsible for generating the signal sleep_s taking as input the signal blink_in. Sleep_s is triggered when the system detects that the driver has closed his eyes continuously for more than 700 ms, approximately. The following schematic, with the signal names according to the entity description

Write a VHDL file (block_c.vhd) with the dataflow description of block_c. It must have the following entity declaration:

entity block_c is Port ( clk : in STD_LOGIC; blink_in : in STD_LOGIC; sleep_out : out STD_LOGIC); end block_c;

fifteen_s block_a accum_s -fatigue_out block_b 12 sleep_s block_d T clk rst danger_out 4 clk rst block_c blink_in clk clk rst blink_in clk D 0 a 0 blink_in clk 1 0 D a blink_in clk 1 D a 0 -sleep_out 0 blink_in clk