Write a VHDL file (fatigue_detector.vhd) with the structural description of the complete circuit shown in the block diagram on the first page.

A car manufacturer is to incorporate a driver fatigue detection system based on the frequency and duration of blinks.

The system consists of the following elements:

1.An oscillator generating a 200 ms period clock signal, clk.

2.A reset signal, rst, active at high level for 300 ms when the car is started.

3.An infrared camera that analyzes the driver's eyes. It has an output, blink_in, which provides a '1' if it detects closed eyes and a '0' otherwise. This signal is synchronous with clk.

4.A visual alarm on the dashboard recommending the driver to rest, and it is triggered by the signal fatigue_out.

5.A loud audible alarm triggered by signal danger_out.

6.An FPGA that receives clk, rst and blink_in and generates fatigue_out and danger_out

Structure of the system like this:

Write a VHDL file (fatigue_detector.vhd) with the structural description of the complete circuit shown in the block diagram on the first page. Use the modules described above(In my other questions). It must have the following entity declaration:

entity fatigue_detector is Port ( clk : in STD_LOGIC; rst : in STD_LOGIC; blink_in : in STD_LOGIC; fatigue_out : out STD_LOGIC; danger_out : out STD_LOGIC); end fatigue_detector;

fifteen_s block_a accum_s -fatigue_out block_b 12 sleep_s block_d T clk rst danger_out 4 clk rst block_c blink_in clk clk rst