Write a VHDL module for the sequential machine of the following table. Use two processes as in the figure below.

Present State	Next State		Present Output
	X = 0	X = 1	X = 0	X = 1
S0	S0	S1	0	0
S1	S2	S1	0	0
S2	S0	S1	0	1

1 entity SM172 is 2 port (X, CLk: in bit 4 end SM172; 5 architecture Table of SM17 2 is Z: out bit); signal State, Nextstate:integer range 0 to 60 7 begin 8 process(State, X) Combinational Circuit begin 10 case State is when 0= > if X = '0, then Z if X = .0' then Z if X = .0, then Z if X = '0' then Z if X = '0then Z Z