Question: Write a VHDL program consisting of a single entity whose architecture is a single process that implments a full adder. That is, a circuit with

Write a VHDL program consisting of a single entity whose architecture is a single process that implments a full adder. That is, a circuit with the following truth table:

inputs | outputs

--------------------------+---------------

a_in b_in carry_in | sum carry_out

--------------------------+---------------

0 0 0 | 0 0

0 0 1 | 1 0

0 1 0 | 1 0

0 1 1 | 0 1

1 0 0 | 1 0

1 0 1 | 0 1

1 1 0 | 0 1

1 1 1 | 1 1

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