// Write an equals module such that:
	// A, B are 1-wire inputs.
	// Equal, AisLarger, and BisLarger are outputs.
	// Equal = (A == B)
	// AisLarger = (A > B)
	// BisLarger = (B > A)
	// Module heading, you specify the input and outputs in the parameter list
	module equals (A, B, Equal, AisLarger, BisLarger);
	input A, B; // You must label which parameters are inputs
	output Equal, AisLarger, BisLarger;// You must label which paramters are outputs
	// You can create internal wires ("one use variables") for later use
	wire notA, notB; // You will *probably* need more.
	// Now implement your gates, sytax:
	// # ();
	not #1 g1(notA, A);
	not #1 g2(notB, B);
	endmodule
	//Notes:
	// The gate name is optional, but will help with later debuggin, please use a name.
	// The gate delay is also optional, but will be mandatory in future assignments.