Question: Write behavioral Verilog code for 4x1 mux using the assignment state. The module should be named as mux4x1, with 4 bit input Data_in, 2 bit

Write behavioral Verilog code for 4x1 mux using the assignment state. The module should be named as mux4x1, with 4 bit input Data_in, 2 bit select line (Sel) and 1 bit output Y.

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