Write the complete entity and architecture for implementing the following state machine in VHDL using a 2-process state machine. Make sure to include both the entity and architecture declarations. You are also expected to create your own custom data type for keeping track of your states. reset STOP. PRESJED startstop /start stop START_RELEAJCD STOP. RELEASED count Active start stop start Stop START- PRESSED count Active Write the complete entity and architecture for implementing the following state machine in VHDL using a 2-process state machine. Make sure to include both the entity and architecture declarations. You are also expected to create your own custom data type for keeping track of your states. reset STOP. PRESJED startstop /start stop START_RELEAJCD STOP. RELEASED count Active start stop start Stop START- PRESSED count Active