Write the Verilog code for a memory module that holds 2K bytes. The memory is byte addressable. Each word is 32-bit wide. There are separate read and write data ports. It has only one address port. This memory has only one enable, called rnw. When rnw is low, a word write takes place on the next positive edge of the clock. When rnw is high, the content of memory word at given address is placed on the data port. On a reset, each memory location is initialized to 0