Question: write Verilog code to implement 16-bit ripple carry adder using Full adders. Use Testbench to validate your design by adding two numbers like 2(2=0000000000000010) and

write Verilog code to implement 16-bit ripple carry adder using Full adders. Use Testbench to validate your design by adding two numbers like 2(2=0000000000000010) and 3(3=0000000000000011). post a screenshot of EDA running your Testbench code

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