You are designing a write buffer between a write$-$through L$1$ cache and a write$-$back L$2$ cache. The L$2$ cache write data bus is $16$ B wide and can per form a write to an independent cache address every $4$ processor cycles. a$.[12]<2\mathrm{.}2>$ How many bytes wide should each write buffer entry be$?$ b$.[15]<2\mathrm{.}2>$ What speedup could be expected in the steady state by using a merging write buffer instead of a nonmerging buffer when zeroing memory by the execution of $64-$bit stores if all other instructions could be issued in parallel with the stores and the blocks are present in the L$2$ cache? c$.[15]<2\mathrm{.}2>$ What would the effect of possible L$1$ misses be on the number of required write buffer entries for systems with blocking and nonblocking caches?