You are given the assembly code shown below, and it is run on the MIPS processor with a 5 stage pipeline shown below. 0x7C add $t1, $t2, $t3 0x80 add $t5, $t4, $t1 a) Explain what kind of hazard is present in the code above, and how many extra cycles are introduced if the MIPS processor has no data-forwarding. Assuming all state elements in the processor are positive edge triggered. b) Assuming the register file is written on the positive edge of the clock, how many cycles would the two instructions take? c) To improve the performance, forwarding is implemented such that the inputs to ALU can be from the Memory stage. Now how many extra cycles are caused by the hazard? How would you modify the part of the datapath shown below for this to be possible? Name any new control signals you have added. You are given the assembly code shown below, and it is run on the MIPS processor with a 5 stage pipeline shown below. 0x7C add $t1, $t2, $t3 0x80 add $t5, $t4, $t1 a) Explain what kind of hazard is present in the code above, and how many extra cycles are introduced if the MIPS processor has no data-forwarding. Assuming all state elements in the processor are positive edge triggered. b) Assuming the register file is written on the positive edge of the clock, how many cycles would the two instructions take? c) To improve the performance, forwarding is implemented such that the inputs to ALU can be from the Memory stage. Now how many extra cycles are caused by the hazard? How would you modify the part of the datapath shown below for this to be possible? Name any new control signals you have added