You have to draw your own k-map.

In this problem inverters have a propagation delay of 2ns,2-input gates have a propagation delay of 2ns, and 3 -input gates have a propagation delay of 6 ns. The vertical lines in the timing diagrams indicate 2ns increments in time. a) Determine the SOP expression for b) Complete the following timing diagram for this circuit with G(A,B,C) in the circuit above. A=B=1. If any potential static-1 hazards found in part a) Complete a K-map and use it in your have produced any glitches in the output then circle the analysis of this circuit for potential glitches in your timing diagram. If there were no glitches, static-1 hazards. Explain the details explicitly say so here. of your findings. c) Add another NAND gate to the d) Complete the timing diagram for your new circuit with A= circuit to address the potential staticB=1. Circle any glitches in the output. If there were no 1 hazard. Draw the new circuit, and glitches, explicitly say so here. label the output of the new NAND gate " H