Question: You need to design a 5-stage pipeline mini-MIPS processor to execute the instruction lw $t3, 0xFFF4($t0). You can design it based on what is introduced

You need to design a 5-stage pipeline mini-MIPS processor to execute the instruction lw $t3, 0xFFF4($t0). You can design it based on what is introduced in the textbook.(textbook Digital design and computer Architecture: David money Harris & Sarah l. harris) You need to answer the following questions when it executes lw $t3, 0xFFF4($t0) (and need to write at least two pages):..

draw the complete microarchitecture of the 5-stage pipeline mini-MIPS processor datapath and control signals needed to execute this instruction...

Describe in words how the datapath works in each stage in executing this instruction...

Describe in words how the control signals work in each stage in executing this instruction...

Describe in words the values of each control signal in executing this instruction...

Describe in words which stage contains the critical path of the datapath, and explain how to compute the cycle time by giving a formula.

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