Design a 5-stage pipeline mini-MIPS processor to execute the

instruction lw $t3, 0xFFF4($t0). You can design it based the figure.

You need to answer following questions when it executes lw $t3,

0xFFF4($t0) (and need to write at least two pages):

1. draw the complete microarchitecture of the 5-stage pipeline

mini-MIPS processor datapath and control signals needed to execute

this instruciton.

2. Describe in words how the datapath works in each stage in executing

this instruction

3. Describe in words how the control signals work in each stage in

executing this instruction

4. Describe in words values of each control signal in executing this instruction

Memory-Mapped 1/0 Code Read the value from I/O Device 1 and place it in $t3 lw $t3, OxFFF4 ($0) Address Decoder CLK WE2 WE 1 WEM CLK RD sel, -01 WE Processor MemWrite Address WriteData Memory CLK 1/0 Device 1 ReadData EN 01 10 1/0 Device 2 8- Cliol to add naton