| Your colleague (a recent Oregon State University graduate) on a cache design team for a...

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| Your colleague (a recent Oregon State University graduate) on a cache design team for a new version of a processor is proposing a cache hierarchy consisting of an 64KiB two-way set associative L1 cache with line size of 64 bytes backed by an inclusive 4MiB four-way set associative L2 cache with a line size of 256 bytes. You patiently explain to them why this can't possibly work and even give them an example. You judiciously refrain from suggesting they should have gone to a better graduate program. a) [10] What was your explanation? b) [10] What example did you use? Hint: You'll need to find five addresses which could all be held L1 but the same lines cannot all be simultaneously held in L2. Assume one of the addresses is Ox0. Show your work. Use the simplest example you can think of. | Your colleague (a recent Oregon State University graduate) on a cache design team for a new version of a processor is proposing a cache hierarchy consisting of an 64KiB two-way set associative L1 cache with line size of 64 bytes backed by an inclusive 4MiB four-way set associative L2 cache with a line size of 256 bytes. You patiently explain to them why this can't possibly work and even give them an example. You judiciously refrain from suggesting they should have gone to a better graduate program. a) [10] What was your explanation? b) [10] What example did you use? Hint: You'll need to find five addresses which could all be held L1 but the same lines cannot all be simultaneously held in L2. Assume one of the addresses is Ox0. Show your work. Use the simplest example you can think of.

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a The proposed cache hierarchy with a 64KiB twoway set associative L1 cache and a 4MiB fourway set a... View the full answer