Your task is to model the following circuit using gate level primitives given the following Verilog module skeleton. Name your gates according to the logic diagram below and use wires properly: Once you have created the cout module, use the given tester to check for correctness and the test results shown on the right should be produced: WHAT TO TURN IN: Once your cout module is working correctly: Copy the contents of your cout module to a file named cout.txt upload cout.txt to the beachboard dropbox for Lab2