(a) Design the circuit shown in Figure P11.44 such that \(v_{O}=v_{D 1}-v_{D 2}=\) \(1 \mathrm{~V}\) when \(v_{1}=-50 \mathrm{mV}\) and \(v_{2}=+50 \mathrm{mV}\). The transistor parameters are \(V_{T N}=0.8 \mathrm{~V}, K_{n}=0.4 \mathrm{~mA} / \mathrm{V}^{2}\), and \(\lambda=0\).

(b) Using the results of part (a), determine the maximum common-mode input voltage.

Transcribed Image Text:

V+ = 10 V RD upl Rp D2 M M2 2 mA V-= -10 V Figure P11.44