Question: Suppose the memory cells at addresses F0 through FD in the machine described in Appendix C contain the following (hexadecimal) bit patterns: Address Contents F0

Suppose the memory cells at addresses F0 through FD in the machine described in Appendix C contain the following (hexadecimal) bit patterns:
Address Contents
F0 ............................. 20
F1 ............................. 00
F2 ............................. 22
F3 ............................. 02
F4 ............................. 23
F5 ............................. 04
F6 ............................. B3
F7 ............................. FC
F8 ............................. 50
F9 ............................. 02
FA ............................. B0
FB ............................. F6
FC ............................. C0
FD ............................. 00
If we start the machine with its program counter containing F0, what is the value in register 0 when the machine finally executes the halt instruction at location FC?

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