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computer science
systems analysis and design 12th
Questions and Answers of
Systems Analysis And Design 12th
Consider the series of CMOS inverters in Figure P16.35. The threshold voltages of the n-channel transistors are \(V_{T N}=0.8 \mathrm{~V}\), and the threshold voltages of the p-channel transistors
(a) A CMOS inverter is biased at \(V_{D D}=2.5 \mathrm{~V}\). The transistor parameters are \(K_{n}=K_{p}=120 \mu \mathrm{A} / \mathrm{V}^{2}, V_{T N}=0.4 \mathrm{~V}\), and \(V_{T P}=-0.4
The transistor parameters in the CMOS inverter are \(V_{T N}=0.35 \mathrm{~V}\), \(V_{T P}=-0.35 \mathrm{~V}, k_{n}^{\prime}=80 \mu \mathrm{A} / \mathrm{V}^{2}\), and \(k_{p}^{\prime}=40 \mu
A CMOS inverter is biased at \(V_{D D}=3.3 \mathrm{~V}\). The transistor threshold voltages are \(V_{T N}=+0.4 \mathrm{~V}\) and \(V_{T P}=-0.4 \mathrm{~V}\). Determine the peak current in the
A load capacitor of \(0.2 \mathrm{pF}\) is connected to the output of a CMOS inverter. Determine the power dissipated in the CMOS inverter for a switching frequency of \(10 \mathrm{MHz}\), for
(a) A CMOS digital logic circuit contains the equivalent of 4 million CMOS inverters and is biased at \(V_{D D}=1.8 \mathrm{~V}\). The equivalent load capacitance of each inverter is \(0.12
A particular IC chip can dissipate \(3 \mathrm{~W}\) and contains 10 million CMOS inverters. Each inverter is being switched at a frequency \(f\). (a) Determine the average power that each inverter
Repeat Problem 16.41 for the case when the chip contains 5 million CMOS inverters being switched at \(f=8 \mathrm{MHz}\) and the total power dissipated can be \(10 \mathrm{~W}\).Data From Problem
Consider a CMOS inverter. (a) Show that when \(v_{I} \cong V_{D D}\), the resistance of the NMOS device is approximately \(1 /\left[k_{n}^{\prime}(W / L)_{n}\left(V_{D D}-V_{T N}\right)\right]\), and
The CMOS inverter in Figure 16.21 is biased at \(V_{D D}=3.3 \mathrm{~V}\). Let \(K_{n}=K_{p}\), \(V_{T N}=0.5 \mathrm{~V}\), and \(V_{T P}=-0.5 \mathrm{~V}\). (a) Determine the two values of
Repeat Problem 16.44 if the circuit and transistor parameters are \(V_{D D}=2.5 \mathrm{~V}\), \(V_{T N}=0.35 \mathrm{~V}, V_{T P}=-0.35 \mathrm{~V}, K_{n}=100 \mu \mathrm{A} / \mathrm{V}^{2}\), and
(a) Determine the noise margins of a CMOS inverter biased at \(V_{D D}=3.3 \mathrm{~V}\) with \((W / L)_{n}=2\) and \((W / L)_{p}=5\). Assume \(V_{T N}=0.4 \mathrm{~V}\) and \(V_{T P}=\) \(-0.4
Consider the three-input CMOS NAND circuit in Figure P16.47. Assume \(k_{n}^{\prime}=2 k_{p}^{\prime}\) and \(V_{T N}=\left|V_{T P}\right|=0.8 \mathrm{~V}\).(a) If \(v_{A}=v_{B}=5 \mathrm{~V}\),
Consider the circuit in Figure P16.48. (a) The inputs \(v_{X}, v_{Y}\), and \(v_{Z}\) listed in the following table are either a logic 0 or a logic 1 . These inputs are the outputs from similar-type
Consider a four-input CMOS NOR logic gate. Determine the \(W / L\) ratios of the transistors to provide for symmetrical switching based on the CMOS inverter design with \((W / L)_{n}=2\) and \((W /
Repeat Problem 16.49 for a four-input CMOS NAND logic gate.Data From Problem 16.49:-Consider a four-input CMOS NOR logic gate. Determine the \(W / L\) ratios of the transistors to provide for
Repeat Problem 16.49 for a three-input CMOS NOR logic gate.Data From Problem 16.49:-Consider a four-input CMOS NOR logic gate. Determine the \(W / L\) ratios of the transistors to provide for
Repeat Problem 16.49 for a three-input CMOS NAND logic gate.Data From Problem 16.49:-Consider a four-input CMOS NOR logic gate. Determine the \(W / L\) ratios of the transistors to provide for
Figure P16.53 shows a classic CMOS logic circuit. (a) What is the logic function performed by the circuit? (b) Design the NMOS network. (c) Determine the transistor \(W / L\) ratios to provide
Figure P16.54 is a classic CMOS logic gate. (a) What is the logic function performed by the circuit? (b) Design the PMOS network. (c) Determine the transistor \(W / L\) ratios to provide symmetrical
Figure P16.55 is a classic CMOS logic gate. (a) What is the logic function performed by the circuit? (b) Design the NMOS network. (c) Determine the transistor \(W / L\) ratios to provide symmetrical
Consider the classic CMOS logic circuit in Figure P16.56. (a) What is the logic function performed by the circuit? (b) Design the PMOS network. (c) Determine the transistor \(W / L\) ratios to
(a) Given inputs \(A, B, C, \bar{A}, \bar{B}\), and \(\bar{C}\), design a CMOS circuit to implement the logic function \(Y=A \bar{B} \bar{C}+\bar{A} \bar{B} C+\bar{A} B \bar{C}\). The design should
(a) Given inputs \(A, B, C, D\), and \(E\), design a CMOS circuit to implement the logic function \(\bar{Y}=A(B+C)+D+E\).(b) Repeat part (b) of Problem 16.57 for this circuit.Data From Problem
(a) Determine the logic function performed by the circuit in Figure P16.59. (b) Determine the \(W / L\) ratios to provide symmetrical switching times equal to the basic CMOS inverter with \((W /
(a) Consider a five-input CMOS NOR logic gate. Design the \(W / L\) ratios of the transistors to provide symmetrical switching times equal to the basic CMOS inverter with \((W / L)_{n}=2\) and \((W /
(a) Figure P16.61 shows a clocked CMOS logic circuit. Make a table showing the state of each transistor ("on" or "off"), and determine the output voltages \(v_{O 1}\) and \(v_{O 2}\) for the input
(a) For the circuit in Figure P16.62, make a table showing the state of each transistor ("on" or "off"), and determine the output voltages \(v_{O 1}, v_{O 2}\), and \(v_{\mathrm{O} 3}\) for the input
Sketch a clocked CMOS domino logic circuit that realizes the function \(Y=A \bar{B}+\bar{A} B\). Assume that both the variable and its complement are available as input signals.
Sketch a clocked CMOS domino logic circuit that realizes the function \(Y=A B+C(D+E)\).
Sketch a clocked CMOS domino logic circuit that realizes the function \(Y=A(B+C)(D+E)\)
Consider the CMOS clocked circuit in Figure 16.44(b). Assume the effective capacitance at the \(v_{O 1}\) terminal is \(25 \mathrm{fF}\). If the leakage current through the \(M_{N A}\) and \(M_{N
The parameters of an NMOS transmission gate are \(V_{T N}=0.4 \mathrm{~V}\), \(K_{n}=0.15 \mathrm{~mA} / \mathrm{V}^{2}\), and \(C_{L}=0.2 \mathrm{pF}\).(a) For a gate voltage of \(\phi=3.3
The NMOS transistors in the circuit shown in Figure P16.68 have parameters \(K_{n}=0.2 \mathrm{~mA} / \mathrm{V}^{2}, V_{T N}=0.5 \mathrm{~V}, \lambda=0\), and \(\gamma=0\).(a) For gate voltages of
Consider the circuit shown in Figure P16.69. The input voltage \(v_{I}\) is either \(0.1 \mathrm{~V}\) or \(2.5 \mathrm{~V}\). Assume gate voltages of \(\phi=2.5 \mathrm{~V}\). The threshold voltages
Consider the circuit in Figure P16.70. What logic function is implemented by this circuit? Are there any potential problems with this circuit? 0 B A Figure P16.70 T OY
What is the logic function implemented by the circuit in Figure P16.71? A o Bo To Bo A Figure P16.71 A AO -OY -OZ
(a) Design an NMOS pass transistor logic circuit to perform the function \(Y=A+B(C+D)\). Assume that both the variable and its complement are available as input signals.(b) Repeat part (a) for the
Consider the circuit in Figure P16.73.(a) Determine the value of \(Y\) for \(\phi=2.5 \mathrm{~V}\) and (i) \(A=B=0\); (ii) \(A=0, B=2.5 \mathrm{~V}\); (iii) \(A=2.5 \mathrm{~V}\), \(B=0\); and (iv)
What is the logic function implemented by the circuit in Figure P16.74? Ao Figure P16.74 OY
Consider the circuit in Figure P16.75. (a) Determine the value of \(Y\) for (i) \(A=B=0\); (ii) \(A=2.5 \mathrm{~V}, B=0\); (iii) \(A=0, B=2.5 \mathrm{~V}\); and (iv) \(A=B=2.5 \mathrm{~V}\). (b)
What is the logic function implemented by the circuit in Figure P16.76? Bo Figure P16.76 PVDD A P2 N OY
The circuit in Figure P16.77 is a form of clocked shift register. Signals \(\phi_{1}\) and \(\phi_{2}\) are nonoverlapping clock signals. Describe the operation of the circuit. Discuss any possible
Consider the NMOS R-S flip-flop in Figure 16.63 biased at \(V_{D D}=2.5 \mathrm{~V}\). The threshold voltages are \(0.4 \mathrm{~V}\) (enhancement-mode devices) and \(-0.6 \mathrm{~V}\)
Figure P16.79 shows two CMOS inverters in cascade. This circuit can be thought of as an uncoupled CMOS R/S flip flop. The transistor parameters are \(K_{n}=K_{p}=0.2 \mathrm{~mA} / \mathrm{V}^{2},
Consider the circuit in Figure P16.80. Determine the state of the outputs for various input signals. What is the purpose of the input signal \(\phi\) ? M VDD Mg M6 M5 b R M M M3 M4 -S Figure P16.80
The circuit in Figure P16.81 is an example of a D flip-flop. (a) Explain the operation of the circuit. Is this a positive- or negative-edge-triggered flipflop? (b) Redesign the circuit to make this a
Show that the circuit in Figure P16.82 is a J-K flip-flop. CLK o Figure P16.82 VDD D Sp CLK RD
Reconsider the circuit shown in Figure P16.48. Show that this circuit is a \(\mathrm{J}-\mathrm{K}\) flip-flop with \(J=v_{X}, K=v_{Y}\), and CLK \(=v_{Z}\). 5 V 5V P2 P4 Ps P1 P3 vy O N N N3 N4 0z
A 256-K memory is organized in a square array and uses the NMOS NOR decoder in Figure 16.73 (b) for the row- and column-decoders.(a) How many inputs does each decoder require?(b) What input to the
(a) A 1 megabit memory is organized in a square with each memory cell being individually addressed. Determine the number of input address lines required for the row and column decoders. (b) If the 1
A 4096-bit RAM consists of 512 words of 8 bits each. Design the memory array to minimize the number of row and column address decoder transistors required. How many row and column address lines are
Assume that an NMOS address decoder can source \(250 \mu \mathrm{A}\) when the output goes high. If the effective capacitance of each memory cell is \(C_{L}=0.8 \mathrm{pF}\) and the effective
Consider the NMOS RAM cell with resistor load in Figure 16.74(b). Assume parameters values of \(k_{n}^{\prime}=80 \mu \mathrm{A} / \mathrm{V}^{2}, V_{T N}=0.4 \mathrm{~V}, V_{D D}=2.5 \mathrm{~V}\),
A 16-K NMOS RAM, with the cell design shown in Figure 16.74(b), is to dissipate no more than \(200 \mathrm{~mW}\) in standby when biased at \(V_{D D}=2.5 \mathrm{~V}\). Design the width-to-length
Consider the CMOS RAM cell and data lines in Figure 16.76 biased at \(V_{D D}=2.5 \mathrm{~V}\). Assume transistor parameters \(k_{n}^{\prime}=80 \mu \mathrm{A} / \mathrm{V}^{2}, k_{p}^{\prime}=35
Consider the CMOS RAM cell and data lines in Figure 16.76 with circuit and transistor parameters described in Problem 16.90. Assume initially that \(Q=0\) and \(\bar{Q}=1\). Assume the row is
Consider a general sense amplifier configuration shown in Figure 16.82 for a dynamic RAM. Assume that each bit line has a capacitance of \(1 \mathrm{pF}\) and is precharged to \(4 \mathrm{~V}\). The
Design a 4-word \(\times\) 4-bit NMOS mask-programmed ROM to produce outputs of \(1011,1111,0110\), and 1001 when rows \(1,2,3\), and 4 , respectively, are addressed.
Design an NMOS \(16 \times 4\) mask-programmed ROM that provides the 4-bit product of two 2-bit variables.
Design an NMOS mask-programmed ROM that decodes a binary input and produces the output for a seven-segment array. The output is to be high when a particular LED is to be turned on.
An analog signal in the range 0 to \(5 \mathrm{~V}\) is to be converted to a digital signal with a quantization error of less than one percent. (a) What is the required number of bits? (b) What input
An analog signal in the range 0 to \(3.3 \mathrm{~V}\) is to be converted to a digital signal with a quantization error of less than 0.5 percent. (a) What is the required number of bits? (b) What
(a) What is the output voltage of the 4-bit weighted-resistor D/A in Figure 16.90 if the input is 0110 ? Assume \(R_{F}=10 \mathrm{k} \Omega\). (b) The input signal changes to 1001 . What is the
Consider the 4-bit weighted-resistor D/A converter in Figure 16.90. Let \(R_{F}=10 \mathrm{k} \Omega\).(a) What is the maximum allowed tolerance ( \(\pm\) percent) in the value of \(R_{1}\) so that
The weighted-resistor D/A converter in Figure 16.90 is to be expanded to an 8bit device. (a) What are the required resistance values of the additional four input resistors? (b) What is the output
The \(N\)-bit \(\mathrm{D} / \mathrm{A}\) converter with an \(R-2 R\) ladder network in Figure 16.92 is to be designed as a 6-bit \(\mathrm{D} / \mathrm{A}\) device. Let \(V_{\mathrm{REF}}=-5.0
The 3-bit flash A/D converter in Figure 16.93 has a reference voltage of \(V_{\mathrm{REF}}=3.3 \mathrm{~V}\). The 3 -bit output is 101 . What is the range of \(v_{A}\) that produces this output?
A 6-bit flash A/D converter, similar to the one in Figure 16.93, is to be fabricated. How many resistors and comparators are required? VREF ww 2 ww R R 190 -ob 0b3 Combinational logic ww ww ww wwww 5
A 10-bit counting A/D converter has an analog input in the range \(0 \leq v_{A} \leq\) \(5 \mathrm{~V}\) and has a clock frequency of \(1 \mathrm{MHz}\). (a) What is the maximum conversion time? (b)
Consider the 10-bit counting A/D converter described in Problem 16.104.(a) What is the output if the analog input is \(v_{A}=3.125 \mathrm{~V}\) ?(b) Repeat part (a) if \(v_{A}=1.8613
Consider the three types of NMOS inverters shown in Figures 16.3(a), 16.5(a), and 16.7(a). Using a computer simulation, investigate the voltage transfer characteristics and the current versus input
Using a computer simulation, investigate the propagation delay time and switching characteristics of a CMOS inverter by setting up a series of CMOS inverters in cascade. Use standard transistors and
Consider a three-input CMOS NAND logic circuit similar to the two-input circuit shown in Figure 16.34(a). Using a computer simulation, investigate the voltage transfer characteristics and switching
Using a computer simulation, investigate the \(Q\) and \(\bar{Q}\) values in the CMOS RAM cell shown in Figure 16.76 during read and write cycles for various transistor width-to-length ratios. In
Design a classic CMOS logic circuit that will implement the logic function \(Y=A \cdot(B+C)+D \cdot E\).
Design clocked CMOS logic circuits that will implement the logic functions (a) \(Y=[A \cdot B+C \cdot D]\) and (b) \(Y=[A \cdot(B+C)+D]\).
Design an NMOS pass logic network that implements the logic functions described in Problem 16.111.Data From Problem 16.111:-Design clocked CMOS logic circuits that will implement the logic functions
Design a clocked CMOS dynamic shift register in which the output becomes valid on the positive-going edge of a clock signal.
Describe the difference between an active filter and a passive filter. What is the primary advantage of an active filter?
Sketch the general characteristics of a low-pass filter, a high-pass filter, and a band-pass filter.
Consider a low-pass filter. What is the slope of the roll-off with frequency for a (a) one-pole filter, (b) two-pole filter, (c) three-pole filter, and (d) four-pole filter?
What characteristic defines a Butterworth filter?
Describe how a capacitor in conjunction with two switching transistors can behave as a resistor.
Sketch a one-pole low-pass switched-capacitor filter circuit.
Explain the two basic principles that must be satisfied in an oscillator circuit.
Describe and explain the operation of a phase-shift oscillator.
Describe and explain the operation of a Wien-bridge oscillator.
Sketch the circuit and characteristics of a basic inverting Schmitt trigger.
What is meant by bistable and astable circuits?
What is the primary advantage of a Schmitt trigger circuit.
Sketch the circuit and explain the operation of a Schmitt trigger oscillator.
Describe how an op-amp in conjunction with a class-AB output stage can be used as a power amplifier.
Sketch a bridge power amplifier and describe its operation.
Sketch the basic circuit block diagram of a voltage regulator and explain the principle of operation.
Define load regulation of a voltage regulator.
Sketch the basic circuit of a series-pass voltage regulator.
(a) Design a single-pole high-pass filter with a gain of 8 in the passband and a \(3 \mathrm{~dB}\) frequency of \(30 \mathrm{kHz}\). The maximum resistance is to be \(210 \mathrm{k} \Omega\).(b)
Consider a Butterworth low-pass filter. Determine the reduction in gain (in \(\mathrm{dB}\) ) at \(f=1.5 f_{3 \mathrm{~dB}}\) for a (a) two-pole, (b) three-pole, (c) four-pole, and (d) five-pole
The specification in a high-pass Butterworth filter design is that the voltage transfer function magnitude at \(f=0.9 f_{3 \mathrm{~dB}}\) is \(6 \mathrm{~dB}\) below the maximum value. Determine the
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