Design a self-bias network using a JFET transistor with IDSS = 8 mA and VP = -6

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Design a self-bias network using a JFET transistor with IDSS = 8 mA and VP = -6 V to have a Q-point at IDQ = 4 mA using a supply of 14 V. Assume that RD = 3RS and use standard values.
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Electronic Devices and Circuit Theory

ISBN: 978-0135026496

10th edition

Authors: Robert L. Boylestad, Louis Nashelsky

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