Determine the worst case input offset voltage for the circuit of Fig 4 58 Assume the worst case I S mismatches in the transistors are plusmn 5 percent and Icirc sup2 F 15 for the pnp transistors Assume the dc output voltage is V SUP V BE(on) Fig 4 58 VSUP Q4 Q3 V, Vo v, Q2 6 V V, v 100 VSUP

Question: Determine the worst-case input offset voltage for the circuit of Fig. 4.58. Assume the worst-case I S mismatches in the transistors are ± 5 percent

Determine the worst-case input offset voltage for the circuit of Fig. 4.58. Assume the worst-case I_Smismatches in the transistors are ± 5 percent and Î²_F= 15 for the pnp transistors. Assume the dc output voltage is V_SUPˆ’ |V_BE(on)|.

Fig. 4.58:

+VSUP Q4 Q3 V, = Vo+v, Q2 +6 V; = V, + v; 100 μΑ -VSUP

+VSUP Q4 Q3 V, = Vo+v, Q2 +6 V; = V, + v; 100 -VSUP

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