Repeat Problem 4.16 except replace the npn and pnp transistors with n-channel and p-channel MOS transistors, respectively. Assume W_n= 50[1]µm and W_p= 100[1]µm. For all transistors, assume L_drwn= 1 µm and X_d= 0. Let I_TAIL= 100 µA. Ignore the body effect. Use Table 2.3 for other parameters.

Table 2.3:

Repeat Problem 4.16:

Determine the unloaded voltage gain ν_o/ν_i and output resistance for the circuit of Fig. 4.59. Neglect r_μ. Verify with SPICE and also use SPICE to plot the large-signal V_O-V_I transfer characteristic for V_SUP = 2.5V.

Figure 4.59:

Value Value p-Channel Transistor n-Channel Units Parameter Symbol Transistor NA, ND 4 x 105 Substrate doping Gate oxide thickness 3 x 1016 Atoms/cm 150 150 fax Metal-silicon work function -0.6 -0.1 cm?/V-s Channel mobility Minimum drawn channel 550 250 Lawn 0.8 0.8 um length Source, drain junction depth Source, drain side diffusion Overlap capacitance per unit gate width X, 0.2 0.3 um 0.18 0.12 um Cad 0.12 0.18 fF/um Threshold adjust implant (b dist) impurity type effective depth effective surface XI 0.2 0.2 um Atoms/cm 3 x 1016 2 x 1016 concentration Nominal threshold voltage Polysilicon gate doping concentration 0.7 -0.7 Atoms/cm 100 Napoly 100 Poly gate sheet resistance Source, drain-bulk junction capacitances (zero bias) Source, drain-bulk junction Rs 10 10 fF/um? Co 0.18 0.30 0.5 0.5 capacitance grading coefficient Source, drain periphery capacitance (zero bias) Source, drain periphery capacitance grading 1.0 2.2 fF/um 0.5 0.5 coefficient Source, drain junction built-in potential 0.65 0.65 Oss Atoms/cm? Surface-state density 10" 101 dX4 Channel-length modulation 0.08 0.04 um/V dVps parameter +VSUP Os Vo+v Q4 1.3 V Q2 V = V + V ITAIL -VSUP