Replace the bipolar transistors in Fig. 7.40 with NMOS transistors. Repeat the calculations in

Problem 7.21, using R_S = 100 kΩ, R_L = 3 kΩ, and the NMOS transistor model data in Problem 7.2, but use C_db = 200 fF and C_sb = 180 fF here. Take I_D1 = 50 µA and I_D2 = 1 mA.

Data from Prob. 7.21:

A Darlington stage and a common-collector€“common-emitter cascade are shown schematically in Fig. 7.40, where R_S = 100 kΩ and R_L = 3 kΩ.

(a) Calculate the low-frequency small-signal voltage gain Ï…_o/Ï…_i for each circuit.

(b) Use the zero-value time-constant method to calculate the ˆ’3-dB frequency of the gain of each circuit. 

Fig. 7.40:

Rg RL Vo V Q2 (a) Rs R1 Q2 Vo (b)