Change your design to minimize the latency, then to minimize the cost. Compare the cost and latency of these two optimized designs.

Cost and latency of digital logic depends on the kinds of basic logic elements (gates) that are available and on the properties of these gates. The remaining three problems in this exercise refer to these gates, latencies, and costs:

a. b. NOT Latency Cost 10ps 20ps 2 2 2-Input AND or OR Latency 12ps 40ps Cost 4 3 Each Additional Input for AND/OR Latency Cost +2ps +30ps +1 +1 D-Element Latency 30ps 80ps Cost 10 9