Question: If LD/ST address computation can overflow, can we delay overflow exception detection into the MEM stage? Use the given store instruction to explain what happens.

If LD/ST address computation can overflow, can we delay overflow exception detection into the MEM stage? Use the given store instruction to explain what happens.

The remaining three problems in this exercise also refer to the following store instruction: SW b. SW a. R5,-40 (R15) R1,0 (R1) Store Instruction

SW b. SW a. R5,-40 (R15) R1,0 (R1) Store Instruction

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