Repeat 4.19.3 but this time determine which of the two options results in shorter time per instruction.

Problem 4.19.3

Let us assume that we cannot afford to have three-input Muxes that are needed for full forwarding. We have to decide if it is better to forward only from the EX/MEM pipeline register (next-cycle forwarding) or only from the MEM/WB pipeline register (two-cycle forwarding). Which of the two options results in fewer data stall cycles?

The remaining three problems in this exercise refer to the following latencies for individual pipeline stages. For the EX stage, latencies are given separately for a processor without forwarding and for a processor with different kinds of forwarding.

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IF ID a. 150ps 100ps b. 300ps EX (no FW) 120ps 200ps 300ps EX (full FW) 150ps 350ps EX (FW from EX/MEM only) 140ps 330ps EX (FW from MEM/WB only) 130ps 320ps MEM WB 120ps 100ps 290ps 100ps