This exercise is intended to help you better understand the last pitfall from failure to consider pipelining in instruction set design. The first four problems in this exercise refer to the following new MIPS instruction:

How would you change the 5-stage MIPS pipeline to add support for micro-op translation needed to support this new instruction?

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a. Instruction SWINC Rt, Offset (Rs) b. SWI Rt, Rd (Rs) Interpretation Mem[Reg[Rs]+Offset]=Reg [Rt] Reg[Rs ] Reg[Rs]+4 Mem[Reg[Rd]+Reg [Rs ]]= Reg[Rt]