This exercise explores how exception handling affects control unit design and processor clock cycle time. The first three problems in this exercise refer to the following MIPS instruction that triggers an exception:

Some of the control signals generated in the ID stage are stored into the ID/EX pipeline register, and some go directly into the EX stage. Explain why, using this instruction as an example.

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a. b. Instruction BNE R1, R2, Label SUB R2, R4, R5 Exception Invalid target address Arithmetic overflow