Using the references from Exercise 5.3, show the final cache contents for a three-way set associative cache with two-word blocks and a total size of 24 words. Use LRU replacement. For each reference identify the index bits, the tag bits, the block offset bits, and if it is a hit or a miss.

This exercise examines the impact of different cache designs, specifically comparing associative caches to the direct-mapped caches from Section 5.2. For these exercises, refer to the table of address streams shown in Exercise 5.3.

Address streams from Exercise 5.3

Direct-mapped caches from Section 5.2

a. b. 3, 180, 43, 2, 191, 88, 190, 14, 181, 44, 186, 253 21, 166, 201, 143, 61, 166, 62, 133, 111, 143, 144, 61