Using the references from Exercise 5.3, what is the miss rate for a fully associative cache with two-word blocks and a total size of 8 words, using LRU replacement? What is the miss rate using MRU (most recently used) replacement? Finally what is the best possible miss rate for this cache, given any replacement policy?

This exercise examines the impact of different cache designs, specifically comparing associative caches to the direct-mapped caches from Section 5.2. For these exercises, refer to the table of address streams shown in Exercise 5.3.

Address streams from Exercise 5.3

Direct-mapped caches from Section 5.2

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a. b. 3, 180, 43, 2, 191, 88, 190, 14, 181, 44, 186, 253 21, 166, 201, 143, 61, 166, 62, 133, 111, 143, 144, 61