We can eliminate the MemRead control signal and have the data memory be read in every cycle, i.e., we can permanently have MemRead=1. Explain why the processor still functions correctly after this change. What is the effect of this change on clock frequency and energy consumption?

The remaining three problems in this exercise assume that components in the datapath have the following latencies. You can assume that the other components of the datapath have negligible latencies.

Transcribed Image Text:

I-Mem a. 200ps b. 750ps Control Register Read or Write 150ps 90ps 500ps 300ps ALU 90ps 250ps D-Mem Read or Write 250ps 500ps