What is the performance impact of your changes from 4.38.3?

Exercise 4.38.3

If energy reduction is paramount, how would you change the pipelined design? What is the percentage reduction in the energy spent by an LW instruction after this change?

The remaining three problems in this exercise assume that components in the datapath have the following latencies. You can assume that the other components of the datapath have negligible latencies.

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I-Mem a. 200ps b. 750ps Control Register Read or Write 150ps 90ps 500ps 300ps ALU 90ps 250ps D-Mem Read or Write 250ps 500ps