- In directory cache coherence protocols, such as those based on MESI or MOESI, a silent transition is one in which a cache line transitions from one state to another without reporting this change to
- For the MOESI protocol, consider any pair of caches. Use the following matrix to indicate which states are permitted for a given cache line; use X for forbidden and checkmark for permitted.
- At a top level, what are the main design variables in a multicore organization?
- Why is there a trend toward giving an increasing fraction of chip area to cache memory?
- The r’s complement of an n-digit number N in base r is defined as rn − N for N ≠ 0 and 0 for N = 0. Find the tens complement of the decimal number 13,250.
- Show in hex notation:a. The packed decimal format for 23.b. The ASCII characters 23.
- What types of locations can hold source and destination operands?
- If an instruction contains four addresses, what might be the purpose of each address?
- What types of operands are typical in machine instruction sets?
- What is meant by the term nesting of procedures?
- In what way are numbers rounded using arithmetic right shift (e.g., round toward + ∞, round toward − ∞, toward zero, away from 0)?
- List three possible places for storing the return address for a procedure return.
- What is a reentrant procedure?
- What is reverse Polish notation?
- Convert the expression A + B − C to postfix notation using Dijkstra’s algorithm. Show the steps involved. Is the result equivalent to (A + B) − C or A + (B − C) ? Does it matter?
- Show the calculation of the expression in Figure E.5, using a presentation similar to Figure E.4. Figure E.5 Conversion of an Expression from Infix to Postfix Notation Input Output Stack (top on
- The MIPS processor can be set to operate in either big-endian or little-endian mode. Consider the Load Byte Unsigned (LBU) instruction, which loads a byte from memory into the low-order 8 bits of a
- Briefly define direct addressing.
- Briefly define register indirect addressing.
- Briefly define relative addressing.
- How many times does the processor need to refer to memory when it fetches and executes an indirect-address-mode instruction if the instruction is(a) A computation requiring a single operand(b) A
- What categories of data are commonly supported by user-visible registers?
- A microprocessor is clocked at a rate of 5 GHz.a. How long is a clock cycle?b. What is the duration of a particular type of machine instruction consisting of three clock cycles?
- In the discussion of Figure 17.2, it was stated that only the first two portions of a window are saved or restored. Why is it not necessary to save the temporary registers? A.temp= B.param Restore
- What are some typical characteristics of a RISC instruction set architecture?
- What is a delayed branch?
- A SPARC implementation has K register windows. What is the number N of physical registers?
- What is instruction-level parallelism?
- Briefly define the following terms:True data dependencyProcedural dependencyResource conflictsOutput dependencyAnti-dependency
- What is the distinction between instruction-level parallelism and machine parallelism?
- What is the purpose of an instruction window?
- What is the relationship between instructions and micro-operations?
- List three types of control signals.
- Briefly explain what is meant by a hardwired implementation of a control unit.
- What is the purpose of a control memory?
- List and briefly define the QPI protocol layers.
- Consider a 32-bit microprocessor, with a 16-bit external data bus, driven by an 8-MHz input clock. Assume that this microprocessor has a bus cycle whose minimum duration equals four input clock
- How many check bits are needed if the Hamming error correction code is used to detect single bit errors in a 1024-bit data word?
- What is the typical disk sector size?
- How is redundancy achieved in a RAID system?
- What is the difference between memory-mapped I/O and isolated I/O?
- What are the major functions of an I/O module?
- When a device interrupt occurs, how does the processor determine which device issued the interrupt?
- What is the sign-extension rule for twos complement numbers?
- How can you form the negation of an integer in twos complement representation?
- Consider the following operation on a binary word. Start with the least significant bit. Copy all bits that are 0 until the first bit is reached and copy that bit, too. Then take the complement of
- What are the four essential elements of a number in floating-point notation?
- Give a reason for the use of guard bits.
- Under computer integer arithmetic, the quotient J/K of two integers J and K is less than or equal to the usual quotient. True or false?
- Apply DeMorgan’s theorem to the following equations:a. F = V + A + Lb. F = A + B + C + D
- We can gain more insight into Little’s law by considering Figure 2.8a. Over a period of time T, a total of C items arrive at a system, wait for service, and complete service. The upper solid line
- List and briefly define the PCIe protocol layers.
- The VAX SBI bus uses a distributed, synchronous arbitration scheme. Each SBI device (i.e., processor, memory, I/O module) has a unique priority and is assigned a unique transfer request (TR) line.
- The microprocessor of Problem 3.14 initiates the fetch operand stage of the increment memory direct instruction at the same time that a keyboard activates an interrupt request line. After how long
- Consider these terms: instruction spatial locality, instruction temporal locality, data spatial locality, data temporal locality. Match each of these terms to one of the following definitions:a.
- What is the general relationship among access time, memory cost, and capacity?
- Consider these two programs:a. The two programs perform the same function. Describe it.b. Which version performs better, and why? for ( i = 1; i < n; i++) { for ( i = 1; i < n; i++) { %3D Z[i] X[i]
- For a system with two levels of cache, define cache access time; cache access time; access time; cache hit ratio; first/second level cache hit ratio. Provide an equation for for a read operation.
- What is the difference between associative cache memory and content-addressable memory?
- For an associative cache, a main memory address is viewed as consisting of two fields. List and define the two fields.
- The Intel 80486 has an on chip, unified cache. It contains 8 kB and has a four-way set-associative organization and a block length of four 32-bit words. The cache is organized into 128 sets. There is
- The level below a cache in the memory hierarchy requires 60 ns to read or write a word of data. If the cache line size is 8 words, how many times does the average line have to be written (counting
- What are two interpretations of the term random-access memory?
- What is the difference between DRAM and SRAM in terms of application?
- What is the difference between DRAM and SRAM in terms of characteristics such as speed, size, and cost?
- What are some applications for ROM?
- What is a parity bit?
- What is DDR RAM?
- What is the difference between NAND and NOR flash memory?
- List and briefly define three newer nonvolatile solid-state memory technologies.
- When a DMA module takes control of a bus, and while it retains control of the bus, what does the processor do?
- What is the difference between a process and a program?
- What is the purpose of swapping?
- If a process may be dynamically assigned to different locations in main memory, what is the implication for the addressing mechanism?
- Is it necessary for all of the pages of a process to be in main memory while the process is executing?
- Must the pages of a process in main memory be contiguous?
- Is it necessary for the pages of a process in main memory to be in sequential order?
- What is the purpose of a translation lookaside buffer?
- The IBM System/370 architecture uses a two-level memory structure and refers to the two levels as segments and pages, although the segmentation approach lacks many of the features described earlier
- Count from 1 to 2010 in the following bases:a. 8b. 6c. 5d. 3
- Order the numbers (1.1)2, (1.4)10, and (1.5)16 from smallest to largest.
- Convert the following binary numbers to their decimal equivalents:a. 11100.011b. 110011.10011c. 1010101010.1
- Convert the following decimal numbers to their binary equivalents:a. 34.75b. 25.25c. 27.1875
- Prove that every real number with a terminating binary representation (finite number of digits to the right of the binary point) also has a terminating decimal representation (finite number of digits
- Express the following octal numbers (number with radix 8) in hexadecimal notation:a. 12b. 5655c. 2550276d. 76545336e. 3726755
- Convert the following binary numbers to their hexadecimal equivalents:a. 1001.1111b. 110101.011001c. 10100111.111011
- In general terms, when does the twos complement operation on an n-bit integer produce the same integer?
- What is the benefit of using biased representation for the exponent portion of a floating-point number?
- Construct the operation XOR from the basic Boolean operations AND, OR, and NOT.
- What are the basic elements of floating-point addition and subtraction?
- Compare Figures 11.9 and 11.12. Why is the C bit not used in the latter?Figure 11.9Figure 11.12 START A + 0, Q-1 0 M Multiplicand Q+ Multiplier Count en = 10 Qo, Q-1 = 01 = 11 AA-M 0 = AA+M
- Given a NOR gate and NOT gates, draw a logic diagram that will perform the three-input AND function.
- Write the Boolean expression for a four-input NAND gate.
- Add an additional line to Figure 12.17 so that it functions as a demultiplexer.Figure 12.17 000 Do A В 001 D1 C- 010 D2 011 D3 100 D4 101 D5 110 D6 111 D7
- Repeat the preceding problem using machine D as the reference machine. How does this affect the relative rankings of the four systems?Data from preceding problemAssume that a benchmark program
- For each of the following examples, determine whether this is an embedded system, explaining why or why not.a. Are programs that understand physics and/or hardware embedded? For example, one that
- What are the four main functions of a computer?
- In Figure 1.6 , indicate the width, in bits, of each data path (e.g., between AC and ALU). Central processing unit (CPU) Arithmetic-logic unit (CA) АС MQ Input- output equipment Arithmetic-logic
- Explain Moore’s law.
- The relative performance of the IBM 360 Model 75 is 50 times that of the 360 Model 30, yet the instruction cycle time is only 5 times as fast. How do you account for this discrepancy?