Essentials Of Computer Organization And Architecture 5th Edition Linda Null, Julia Lobur - Solutions

33. What are the advantages and disadvantages of having a small number of sectors per disk cluster? (Hint: You may want to think about retrieval time and the required lifetime of the archives.)
32. Transfer rate of a disk drive can be no faster than the bit density (bits/track) times the rotational speed of the disk. Figure 7.15 gives a data transfer rate of 112GB/sec. Assume that the average track length of the disk is 5.5 inches. What is the average bit density of the disk?
31. Suppose a disk drive has the following characteristics:1. Six surfaces 2. 953 tracks per surface 3. 256 sectors per track 4. 512 bytes/sector 5. Track-to-track seek time of 6.5ms 6. Rotational speed of 5,400rpm 1.a) What is the capacity of the drive?2.b) What is the access time?3.c) Is this
30. Suppose a disk drive has the following characteristics:1. Six surfaces 2. 16,383 tracks per surface 3. 63 sectors per track 4. 512 bytes/sector 5. Track-to-track seek time of 8.5ms 6. Rotational speed of 7,200rpm 1.a) What is the capacity of the drive?2.b) What is the access time?
29. Suppose a disk drive has the following characteristics:1. Five surfaces 2. 1,024 tracks per surface 3. 256 sectors per track 4. 512 bytes/sector 5. Track-to-track seek time of 8ms 6. Rotational speed of 7,500rpm 1.a) What is the capacity of the drive?2.b) What is the access time?3.c) Is this
28. Suppose a disk drive has the following characteristics:1. Four surfaces 2. 1,024 tracks per surface 3. 128 sectors per track 4. 512 bytes/sector 5. Track-to-track seek time of 5ms 6. Rotational speed of 5,000rpm 1.a) What is the capacity of the drive?2.b) What is the access time?3.c) Is this
27. Do you trust disk drive MTTF figures? Explain.
26. The disk specification in Figure 7.15 gives a data transfer rate of 60MB per second when reading from the disk, and 320MB per second when writing to the disk. Why are these numbers different?(Hint: Think about buffering.)
25. By inspection of the disk specification in Figure 7.15, what can you say about whether the disk drive uses zoned-bit recording?
24. Verify the average latency rate cited in the disk specification of Figure 7.15. Why is the calculation divided by 2?
23. Why do differing systems place disk directories in different track locations on the disk? What are the advantages of using each location that you cited?
22. Why do you think the term random access device is something of a misnomer for disk drives?
21. Define the terms seek time, rotational delay, and transfer time.Explain their relationship.
20. If each interval shown in Figure 7.11 is 50ns, how long would it take to transfer 10 bytes of data? Devise a bus protocol, using as many control lines as you need, that would reduce the time required for this transfer to take place. What happens if the address lines are eliminated and the data
19. We pointed out that I/O buses do not need separate address lines. Construct a timing diagram similar to Figure 7.11 that describes the handshake between an I/O controller and a disk controller for a write operation. (Hint: You will need to add a control signal.)
18. With regard to Figure 7.11 and Exercise 17, we have not provided for any type of error handling, such as if the address on the address lines were invalid, or if the memory couldn’t be read because of a hardware error. What could we do with our bus model to provide for such events?
16. If an address bus needs to be able to address eight devices, how many conductors will be required? What if each of those devices also needs to be able to talk back to the I/O control device?
15. Why are I/O buses provided with clock signals?
14. Of programmed I/O, interrupt-driven I/O, DMA, or channel I/O, which is most suitable for processing the I/O of a:1.a) Mouse 2.b) Game controller 3.c) CD 4.d) Thumb drive or memory stick Explain your answers.
13. A generic DMA controller consists of the following components:1. Address generator 2. Address bus interface 3. Data bus interface 4. Bus requestor 5. Interrupt signal circuits 6. Local peripheral controller The local peripheral controller is the circuitry that the DMA uses to select among the
12. A CPU with interrupt-driven I/O is busy servicing a disk request. While the CPU is midway through the disk-service routine, another I/O interrupt occurs.1.a) What happens next?2.b) Is it a problem?3.c) If not, why not? If so, what can be done about it?
11. Name the four types of I/O architectures. Where are each of these typically used, and why are they used there?
10. Amdahl’s Law is as applicable to software as it is to hardware.An oft-cited programming truism states that a program spends 90%of its time executing 10% of its code. Thus, tuning a small amount of program code can often have an enormous effect on the overall performance of a software product.
9. How would you answer Exercise 8 if the system activity consists of 55% processor time and 45% disk activity?
8. Suppose the daytime processing load consists of 60% CPU activity and 40% disk activity. Your customers are complaining that the system is slow. After doing some research, you learn that you can upgrade your disks for $8,000 to make them 2.5 times as fast as they are currently. You have also
7. Your friend has just bought a new personal computer. She tells you that her new system runs at 1GHz, which makes it more than three times faster than her old 300MHz system. What would you tell her? (Hint: Consider how Amdahl’s Law applies.)
6. Suppose that you are designing an electronic musical instrument. The prototype system occasionally produces off-key notes, causing listeners to wince and grimace. You have determined that the cause of the problem is that the system becomes overwhelmed in processing the complicated input. You are
5. Suppose that you are designing a game system that responds to players’ pressing buttons and toggling joysticks. The prototype system is failing to react in time to these input events, causing noticeable annoyance to the gamers. You have calculated that you need to improve overall system
4. Suppose your company has decided that it needs to make certain busy servers 30% faster. Processes in the workload spend 70% of their time using the CPU and 30% on I/O. In order to achieve an overall system speedup of 30%:1.a) How much faster does the CPU need to be?2.b) How much faster does the
3. Suppose your company has decided that it needs to make certain busy servers 50% faster. Processes in the workload spend 60% of their time using the CPU and 40% on I/O. In order to achieve an overall system speedup of 25%:1.a) How much faster does the CPU need to be?2.b) How much faster does the
2. Calculate the overall speedup of a system that spends 40% of its time in calculations with a processor upgrade that provides for 100% greater throughput.
1. Calculate the overall speedup of a system that spends 65% of its time on I/O with a disk upgrade that provides for 50% greater throughput.
30. Look up a specific vendor’s specifications for memory, and report the memory access time, cache access time, and cache hit rate (and any other data the vendor provides).
29. Name two ways that, as a programmer, you can improve cache performance.
28. Pick a specific architecture (other than the one covered in this chapter). Do research to find out how your chosen architecture approaches the concepts introduced in this chapter, as was done for Intel’s Pentium.
27. Consider a system that has multiple processors where each processor has its own cache, but main memory is shared among all processors.1.a) Which cache write policy would you use?2.b) The cache coherency problem. With regard to the system just described, what problems are caused if a processor
26.a) If you are a computer builder trying to make your system as price-competitive as possible, what features and organization would you select for its memory hierarchy?1.b) If you are a computer buyer trying to get the best performance from a system, what features would you look for in its memory
25. A system implements a paged virtual address space for each process using a one-level page table. The maximum size of virtual address space is 16MB. The page table for the running process includes the following valid entries (the → notation indicates that a virtual page maps to the given page
24. Does a TLB miss always indicate that a page is missing from memory? Explain.
23. Given a virtual memory system with a TLB, a cache, and a page table, assume the following:1. A TLB hit requires 5ns.2. A cache hit requires 12ns.3. A memory reference requires 25ns.4. A disk reference requires 200ms (this includes updating the page table, cache, and TLB).5. The TLB hit ratio is
21. 21. Suppose we have 2 bytes of virtual memory and 2 bytes of physical main memory. Suppose the page size is 2 bytes.1.a) How many pages are there in virtual memory?2.b) How many page frames are there in main memory?3.c) How many entries are in the page table for a process that uses all of
14. Consider a byte-addressable computer with 24-bit addresses, a cache capable of storing a total of 64KB of data, and blocks of 32 bytes. Show the format of a 24-bit memory address for:1.a) direct mapped 2.b) associative 3.c) 4-way set associative 15. *15. Suppose a byte-addressable computer
13. A direct-mapped cache consists of 8 blocks. Byte-addressable main memory contains 4K blocks of 8 bytes each. Access time for the cache is 22ns, and the time required to fill a cache slot from main memory is 300ns. (This time allows us to determine that the block is missing and bring it into
10. Suppose a byte-addressable computer using set-associative cache has 2 bytes of main memory and a cache of 64 blocks, where each cache block contains 4 bytes.1.a) If this cache is 2-way set associative, what is the format of a memory address as seen by the cache; that is, what are the sizes of
9. Suppose a byte-addressable computer using set-associative cache has 2 bytes of main memory and a cache of 32 blocks, and each cache block contains 8 bytes.1.a) If this cache is 2-way set associative, what is the format of a memory address as seen by the cache; that is, what are the sizes of the
8. 8. A 2-way set-associative cache consists of four sets. Main memory contains 2K blocks of 8 bytes each and byte addressing is used.1.a) Show the main memory address format that allows us to map addresses from main memory to cache. Be sure to include the fields as well as their sizes.2.b) Compute
7. Assume that a system’s memory has 128M bytes. Blocks are 64 bytes in length, and the cache consists of 32K blocks. Show the format for a main memory address assuming a 2-way setassociative cache mapping scheme and byte addressing. Be sure to include the fields as well as their sizes.
6. 6. Suppose a computer using fully associative cache has 2 bytes of byte-addressable main memory and a cache of 128 blocks, where each block contains 64 bytes.1.a) How many blocks of main memory are there?2.b) What is the format of a memory address as seen by cache;that is, what are the sizes of
5. Suppose a computer using fully associative cache has 2 bytes of byte-addressable main memory and a cache of 128 blocks, where each cache block contains 64 bytes.1.a) How many blocks of main memory are there?2.b) What is the format of a memory address as seen by the cache; that is, what are the
4. Suppose a computer using fully associative cache has 2 bytes of byte-addressable main memory and a cache of 64 blocks, where each cache block contains 32 bytes.1.a) How many blocks of main memory are there?2.b) What is the format of a memory address as seen by the cache; that is, what are the
3. 3. Suppose a computer using direct-mapped cache has 2 bytes of byte-addressable main memory and a cache size of 512 bytes, and each cache block contains 64 bytes.1.a) How many blocks of main memory are there?2.b) What is the format of a memory address as seen by cache;that is, what are the sizes
2. 2. Suppose a computer using direct-mapped cache has 2 bytes of byte-addressable main memory and a cache of 1024 blocks, where each cache block contains 32 bytes.1.a) How many blocks of main memory are there?2.b) What is the format of a memory address as seen by the cache; that is, what are the
1. Suppose a computer using direct-mapped cache has 2 bytes of byte-addressable main memory and a cache of 32 blocks, where each cache block contains 16 bytes.1.a) How many blocks of main memory are there?2.b) What is the format of a memory address as seen by the cache; that is, what are the sizes
29. 29. Suppose an instruction takes four cycles to execute in a nonpipelined CPU: one cycle to fetch the instruction, one cycle to decode the instruction, one cycle to perform the ALU operation, and one cycle to store the result. In a CPU with a four-stage pipeline, that instruction still takes
28. 28. The memory unit of a computer has 256K words of 32 bits each. The computer has an instruction format with four fields: an opcode field; a mode field to specify one of seven addressing modes;a register address field to specify one of 60 registers; and a memory address field. Assume an
27. ◆27. A digital computer has a memory unit with 24 bits per word.The instruction set consists of 150 different operations. All instructions have an operation code part (opcode) and an address part (allowing for only one address). Each instruction is stored in one word of memory.1.a) How many
26. 26. Write code to implement the expression A = (B + C) × (D + E)on three-, two-, one-, and zero-address machines. In accordance with programming language practice, computing the expression should not change the values of its operands.
24. 24. A nonpipelined system takes 100ns to process a task. The same task can be processed in a five-stage pipeline with a clock cycle of 20ns. Determine the speedup ratio of the pipeline for 100 tasks. What is the theoretical speedup that could be achieved with the pipeline system over a
23. 23. A nonpipelined system takes 200ns to process a task. The same task can be processed in a five-segment pipeline with a clock cycle of 40ns. Determine the speedup ratio of the pipeline for 200 tasks. What is the maximum speedup that could be achieved with the pipeline unit over the
20. 20. What is the difference between using direct and indirect addressing? Give an example.
19. 19. Given 16-bit instructions, is it possible to use expanding opcodes to allow the following to be encoded assuming we have a total of 32 registers? If so, show the encoding. If not, explain why is it not possible.1. 60 instructions with two register operands 2. 30 instructions with one
18. 18. Suppose a computer has an instruction format with space for an opcode and either three register values or one register value and an address. What are the various instruction formats that could be used for an ADD instruction on this machine?
17. 17.a) In a computer instruction format, the instruction length is 11 bits and the size of an address field is 4 bits. Is it possible to have 1. 5 two-address instructions 2. 45 one-address instructions 3. 32 zero-address instructions 4. using the specified format? Justify your answer.1.b)
15. 15. Explain how a stack is used to evaluate the RPN expressions from Exercise 13.
14. 14. Convert the following expressions from reverse Polish notation to infix notation.1.a) W X Y Z − + ×2.b) U V W X Y Z + × + × +3.c) X Y Z + V W − × Z + +
13. 13. Convert the following expressions from reverse Polish notation to infix notation.1.a) 12 8 3 1 + − /2.b) 5 2 + 2 × 1 + 2 ×3.c) 3 5 7 + 2 1 − × 1 + +
12. 12. Convert the following expressions from infix to reverse Polish(postfix) notation.1. ◆a) X × Y + W × Z + V × U 2.b) W × X + W × (U × V + Z )3.c) (W × (X + Y × (U × V )))/(U × (X + Y ))
11. 11. Convert the following expressions from infix to reverse Polish(postfix) notation.1.a) (8 − 6)/2 2.b) (2 + 3) × 8/10 3.c) (5 × (4 + 3) × 2 − 6)
10. ◆10. A computer has 32-bit instructions and 12-bit addresses.Suppose there are 250 two-address instructions. How many oneaddress instructions can be formulated? Explain your answer.
9. 9. There are reasons for machine designers to want all instructions to be the same length. Why is this not a good idea on a stack machine?
8. 8. The Population Studies Institute monitors the population of the United States. In 2008, this institute wrote a program to create files of the numbers representing populations of the various states, as well as the total population of the United States. This program, which runs on a Motorola
7. 7. What kinds of problems do you think endian-ness can cause if you wished to transfer data from a big endian machine to a little endian machine? Explain.
6. ◆6. The first two bytes of a 2M × 16 main memory have the following hex values:1. Byte 0 is FE 2. Byte 1 is 01 If these bytes hold a 16-bit two’s complement integer, what is its actual decimal value if:1.a) Memory is big endian?2.b) Memory is little endian?
2. 2. Show how the following values would be stored by byteaddressable machines with 32-bit words, using little endian and then big endian format. Assume that each value starts at address 10 . Draw a diagram of memory for each, placing the appropriate values in the correct (and labeled) memory
1. 1. Assume you have a byte-addressable machine that uses 32-bit integers and you are storing the hex value 1234 at address 0:1. ◆a) Show how this is stored on a big endian machine.2. ◆b) Show how this is stored on a little endian machine.3.c) If you wanted to increase the hex value to 123456,
To what power of 10 does the prefix giga- refer? What is the(approximate) equivalent power of 2?
To what power of 10 does the prefix micro- refer? What is the(approximate) equivalent power of 2?
State Moore’s Law.
What are the key characteristics of cloud computing?
Respond to the idea presented in Section 1.5: If invented today, what name do you think would be given to the computer?Give at least one good reason for your answer.
Suppose a transistor on an integrated circuit chip were 2 microns in size. According to Moore’s Law, how large would that transistor be in two years? How is Moore’s Law relevant to programmers?
The technologist’s notion of Moore’s Law is that the number of transistors per chip doubles approximately every 18 months. In the 1990s, Moore’s Law started to be described as the doubling of microprocessor power every 18 months. Given this new variation of Moore’s Law, answer the
Do you think that double-dabble is an easier method than the other binary-to-decimal conversion methods explained in this chapter?Why?
With reference to the previous question, what are the drawbacks of the other two conversion methods?
What is normalization, and why is it necessary?
How do cyclic redundancy checks work?
What is a burst error?
Name an error-detection method that can compensate for burst errors.
Perform the following base conversions using subtraction or division-remainder:a) 458 = _________3b) 677 = _________5c) 1518 = _________7d) 4401 = _________9
Perform the following base conversions using subtraction or division-remainder:a) 588 = _________10b) 2254 = _________10c) 652 = _________10d) 3104 = _________10
Perform the following base conversions using subtraction or division-remainder:a) 137 = _________10b) 248 = _________10c) 387 = _________10d) 633 = _________10
Perform the following base conversions:a) 20101 = _________10b) 2302 = _________10c) 1605 = _________10d) 687 = _________10
Perform the following base conversions:a) 20012 = _________10b) 4103 = _________10c) 3236 = _________10d) 1378 = _________10
Perform the following base conversions:a) 21200 = _________10b) 3244 = _________10c) 3402 = _________10d) 7657 = _________10
Convert the hexadecimal number AC12 to binary.
Convert the hexadecimal number 7A01 to binary.
Convert the hexadecimal number DEAD BEEF to binary.
Represent the following decimal numbers in binary using 8-bit signed magnitude, one’s complement, two’s complement, and excess-127 representations:a) 60b) −60c) 20d) −20
Represent the following decimal numbers in binary using 8-bit signed magnitude, one’s complement, two’s complement, and excess-127 representations:a) 89b) −89c) 66d) −66
From the results of the previous two questions, generalize the range of values (in decimal) that can be represented in any given x number of bits using:a) Signed magnitudeb) One’s complementc) Two’s complement

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Essentials Of Computer Organization And Architecture 5th Edition Linda Null, Julia Lobur - Solutions

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